MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation

ABSTRACT

Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

CROSS-REFERENCE TO RELATED APPLICATION

This application contains subject matter similar to subject matterdisclosed in co-pending U.S. patent application Ser. No. 09/386,466,filed on Aug. 31, 1999.

FIELD OF THE INVENTION

The present invention relates to a method of manufacturing high-densityintegrated circuit semiconductor devices exhibiting reliable, adherent,low resistance, well-aligned contacts to source, drain, and gateelectrode regions of active devices, such as MOS transistors formed inor on a semiconductor substrate, by utilizing self-aligned, refractorymetal suicide (“salicide”) processing methodology. The present inventionhas particular utility in manufacturing high-density integrationsemiconductor devices, including multi-level devices, with design rulesof 0.18 μm and below, e.g., 0.15 μm and below.

BACKGROUND OF THE INVENTION

The escalating requirements for high density and performance associatedwith ultra-large scale integration (ULSI) devices necessitate designrules of 0.18 μm and below, such as 0.15 μm and below, with increasedtransistor and circuit speeds, high reliability, and increasedmanufacturing throughput. The reduction of design features, e.g., ofsource, drain, and gate regions of transistors formed in or on a commonsemiconductor substrate, challenges the limitations of conventionalcontact and interconnection technology, including conventionalphotolithographic, etching, and deposition techniques.

As a result of the ever-increasing demand for large-scale andultra-small dimensioned integrated semiconductor devices, self-alignedtechniques have become the preferred technology for forming such devicesin view of their simplicity and capability of high-density integration.As device dimensions decrease in the deep sub-micron range, bothvertically and laterally, many problems arise, especially those causedby an increase in sheet resistance of the contact areas to the sourceand drain regions and junction leakage as junction layer thicknessdecreases. To overcome this problem, the use of self-aligned, highlyelectrically conductive refractory metal suicides, i.e., salicides, hasbecome commonplace in the manufacture of integrated circuitsemiconductor devices comprising, e.g., MOS type transistors. Anothertechnique employed in conjunction with refractory metal silicidetechnology is the use of lightly-doped source and drain extensionsformed just at the edge of the gate region, while more heavily-dopedsource and drain regions, to which ohmic contact is to be provided, arelaterally displaced away from the gate by provision of sidewall spacerson opposing sides of the gate electrode.

Salicide processing involves deposition of a metal that forms anintermetallic compound with silicon, but does not react with siliconoxides, nitrides, or oxynitrides under normal processing conditions.Refractory metals commonly employed in salicide processing includeplatinum (Pt), titanium (Ti), nickel (Ni), and cobalt (Co), each ofwhich forms very low resistivity phases with silicon (Si), e.g., PtSi₂,TiSi₂, NiSi, and CoSi₂. In practice, the refractory metal is depositedin uniform thickness over all exposed upper surface features of a Siwafer, preferably by means of physical vapor deposition (PVD) from anultra-pure sputtering target and an ultra-high vacuum, multi-chamber DCmagnetron sputtering system. In MOS transistor formation, deposition isgenerally performed after gate etch and source/drain junction formation.In a less common variant, source/drain junction formation is effectedsubsequent to refractory metal layer deposition via dopant diffusionthrough the refractory metal layer into the underlying semiconductor. Ineither case, after deposition, the refractory metal layer blankets thetop surface of the gate electrode, typically formed of heavily-dopedpolysilicon, the silicon oxide, nitride, or oxynitride sidewall spacerson the opposing side surfaces of the gate electrode, the silicon oxideisolation regions formed in the silicon substrate between adjacentactive device regions, and the exposed surfaces of the substrate wherethe source and drain regions are formed or will be subsequently formed.As a result of thermal processing, e.g., a rapid thermal annealingprocess (RTA) performed in an inert atmosphere, the refractory metalreacts with underlying Si to form electrically conductive silicide layerportions on the top surface of the polysilicon gate electrode and on theexposed surfaces of the substrate where source and drain regions are orwill be formed. Unreacted portions of the refractory metal layer, e.g.,on the silicon oxide, nitride, or oxynitride sidewall spacers and thesilicon oxide isolation regions, are then removed, as by a wet etchingprocess selective to the metal silicide portions. In some instances,e.g., with Co, a first RTA step may be performed at a relatively lowertemperature in order to form first-phase CoSi which is then subjected toa second RTA step performed at a relatively high temperature to convertthe first-phase CoSi to second-phase, lower resistivity CoSi₂.

Illustrated in FIGS. 1(A)-1(E) are steps in a typical salicide process,illustratively CoSi₂, for manufacturing MOS transistors and CMOS devicesaccording to one process scheme of the conventional art. The term“semiconductor substrate” as employed throughout the present disclosureand claims, denotes a Si-containing wafer, e.g., a monocrystalline Siwafer, or an epitaxial Si-containing layer formed on a semiconductorsubstrate and comprising at least one region 1 of a first conductivitytype. It will be appreciated that for P-MOS transistors, region 1 isn-type and for N-MOS transistors, region 1 is p-type. It is furtherunderstood that the substrate may comprise pluralities of n- and p-typeregions arrayed in a desired pattern, as, for example, in CMOS devices.

Referring more particularly to FIG. 1(A), reference numeral 1 indicatesa region or portion of a Si-containing semiconductor substrate of afirst conductivity type (p or n), fabricated as a MOS transistorprecursor 2 for use in a salicide process scheme. Precursor 2 isprocessed, as by conventional techniques not described here in detail,in order to not unnecessarily obscure the primary significance of thefollowing description. Precursor 2 comprises a plurality of,illustratively two, isolation regions 3 and 3′ of a silicon oxide, e.g.,shallow trench isolation (STI) regions, extending from the substratesurface 4 to a prescribed depth below the surface. A gate insulatorlayer 5, typically comprising a silicon oxide layer about 25-50 Å thick,is formed on substrate surface 4. Gate electrode 6, typically ofheavily-doped polysilicon, is formed over a portion of silicon oxidegate insulator layer 5, and comprises opposing side surfaces 6′, 6′, andtop surface 6″. Blanket layer 7 of an insulative material, typically anoxide, nitride, or oxynitride of silicon, is then formed to cover allexposed portions of substrate surface 4 and the exposed surfaces of thevarious features formed thereon or therein, inter alia, the opposingside surfaces 6′, 6′ and top surface 6″ of gate electrode 6 and theupper surface of STI regions 3, 3′. The thickness of blanket insulativelayer 7 is selected so as to provide sidewall spacers 7′, 7′ of desiredwidth (see below) on each of the opposing side surfaces 6′, 6′ of thegate electrode 6.

Referring now to FIG. 1(B), MOS precursor structure 2 is then subjectedto an anisotropic etching process, as by reactive plasma etchingutilizing a fluorocarbon- or fluorohydrocarbon-based plasma comprisingargon (Ar) and at least one reactive gaseous species selected from CF₄and CHF₃, for selectively removing the laterally extending portions ofinsulative layer 7 and underlying portions of the gate oxide layer 5,whereby sidewall spacers 7′, 7′ of desired width profile are formedalong the opposing side surfaces 6′, 6′ of gate electrode 6.

Adverting to FIG. 1(C), moderately- to heavily-doped source and drainjunction regions 8 and 9 of conductivity type opposite that of thesubstrate or epitaxial layer on a suitable substrate are then formed insubstrate region 1, as by conventional ion implantation (the details ofwhich are omitted for brevity), with sidewall spacers 7′, 7′ acting asimplantation masks and setting the lateral displacement length ofmoderately- to heavily-doped source/drain regions 8 and 9 from therespective proximal edges 6′, 6′ of gate electrode 6.

With reference to FIG. 1(D), in a following step, the structurethus-formed with implanted moderately- to heavily-doped source/drainregions 8, 9 is subjected to a conventional high temperature treatment,typically rapid thermal annealing (RTA), for effecting activation anddiffusion of the implanted dopant species, thereby also forming lightlydoped, shallower depth source/drain extension regions 8′, 9′ laterallyextending from the respective proximal edges of the moderately- toheavily-doped source/drain regions 8, 9 to just beneath the neighboringedge 6′ of gate electrode 6. The above-described method for formingsource/drain regions including lightly-doped extensions is merelyillustrative: i.e., equivalent source/drain structures may be formed byalternative process schemes, e.g., by first lightly implanting substrate1 with dopant impurities of second conductivity type, with the implantedregions extending to just beneath the respective edges of the gateelectrode, followed by selective heavy implantation of the lightly-dopedimplant to form heavily-doped source/drain regions appropriately spacedfrom the gate electrode by the lightly-doped (extension) implants.

With continued reference to FIG. 1(D), a layer 10 of a refractory metalmetal, typically Pt, Co, Ni, or Ti, is then formed, as by DC sputtering,to cover the exposed upper surfaces of precursor 2. Following refractorymetal layer 10 deposition, a thermal treatment, typically rapid thermalannealing (RTA), is performed at a temperature and for a time sufficientto convert metal layer 10 to the corresponding electrically conductivemetal silicide, e.g., PtSi₂, CoSi₂, NiSi, or TiSi₂. Since the refractorymetal silicide forms only where metal layer 10 is in contact with theunderlying silicon, the unreacted portions of metal layer 10 formed overthe silicon oxide isolation regions 3 and 3′ and silicon nitridesidewall spacers 7, 7′ are selectively removed, as by a wet etchprocess.

Referring now to FIG. 1(E), the resulting structure after reaction andremoval of unreacted metal comprises metal silicide layer portions 11and 12, 12′ respectively formed over gate electrode 6 and heavily-dopedsource and drain regions 8 and 9. Further processing may include, interalia, formation of metal contact and dielectric insulator layers.However, as is evident from FIG. 1(E), the lower surfaces of the metalsilicide layer 12, 12′ portions formed by the above-describedmethodology are rough at the silicide-silicon interfaces,disadvantageously resulting in penetration of the underlying siliconsubstrate 1 by the silicide portions 12, 12′. Such penetration or“spiking” of the silicon in the region below the source and drainjunction regions 8 and 9, illustratively shown at 13 and 13′, can causelocal shorting of the junctions, thereby resulting in junction leakage.The effect of junction penetration or spiking is greatest with metalssuch as Co, which have relatively high silicon consumption ratios.Junction penetration or spiking can be moderated or at least minimizedand improved junction integrity provided by increasing the junctiondepth of source and drain regions 8 and 9 or by providing a thinnerrefractory metal layer, thereby reducing silicon consumption duringsilicidation. However, neither of these alternatives is satisfactory:the former approach runs counter to the trend toward smaller devicedimensions, both vertically and laterally, in order to increasetransistor switching speeds, and the latter approach results in anincrease in metal silicide sheet resistance attendant its decrease inthickness.

A number of techniques for reducing leakage in ultra-shallow junctionsemployed in MOSFET type semiconductor devices have been proposed, suchas are disclosed in U.S. Pat. Nos. 4,835,112; 5,208,472; 5,536,684; and5,691,212. Such techniques, however, materially add to processcomplexity and include such steps as germanium implantation to retarddopant diffusion, provision of multiple dielectrics at the edges of thegate electrode, formation of a CoSi₂ —TiN_(x), bi-layer followed byremoval of the TiN_(x) layer and ion implantation of the remaining CoSi₂layer, and formation of an amorphous silicon layer on a silicon MOSprecursor and subsequent implantation, oxidation, annealing, etc.,steps.

Thus, there exists a need for a simplified methodology for formingself-aligned silicide (i.e., salicide) contacts to ultra-thin transistorsource and drain regions which provide low contact sheet resistance,absence of spiking, at least minimal junction leakage, and easycompatibility with conventional process flow for the manufacture ofMOS-based semiconductor devices, e.g., CMOS devices. Moreover, thereexists a need for an improved process for fabricating high quality, lowjunction leakage MOS transistor-based devices which provides increasedmanufacturing throughput and product yield.

DISCLOSURE OF THE INVENTION

An advantage of the present invention is a method of manufacturing ahigh density, sub-micron dimensioned integrated semiconductor devicewith an improved self-aligned contact structure.

Another advantage of the present invention is a method of formingMOS-based semiconductor devices and transistors with metalsilicide-contacted shallow source and drain regions exhibiting very lowjunction leakage.

Still another advantage of the present invention is a method of removingundesired contaminants and residues from silicon semiconductor surfacesprior to refractory metal layer deposition thereon for silicidationreaction therewith.

Yet another advantage of the present invention is a MOS transistorhaving very low sheet resistance self-aligned metal silicide contactsand ultra-shallow source and drain junction regions with very lowjunction leakage.

Additional advantages and other features of the present invention willbe set forth in part in the description which follows and in part willbecome apparent to those having ordinary skill in the art uponexamination of the following or may be learned from the practice of thepresent invention. The advantages of the present invention may berealized and obtained as particularly pointed out in the appendedclaims.

According to an aspect of the present invention, the foregoing and otheradvantages are achieved in part by a method of manufacturing asemiconductor device, which method comprises the steps of:

(a) providing a semiconductor substrate of a first conductivity type andhaving a surface;

(b) forming a thin gate insulator layer in contact with the substratesurface;

(c) forming a gate electrode on a portion of the gate insulator layer,the gate electrode comprising first and second opposing side surfacesand a top surface;

(d) forming a blanket layer of an insulative material on the exposedportions of the thin gate insulator layer on the substrate surface andon the first and second opposing side surfaces and the top surface ofthe gate electrode;

(e) selectively removing, by anisotropically etching, (1) the blanketlayer of insulative material and underlying portions of the thin gateinsulator layer from the substrate surface, and (2) the blanket layer ofinsulative material from the top surface of the gate electrode, therebyforming a tapered insulative sidewall spacer on each of the first andsecond opposing side surfaces of the gate electrode, with portions ofthe thin gate insulator layer remaining below the wider bottom ends ofthe tapered sidewall spacers adjacent the substrate surface and exposedportions of the substrate surface being formed adjacent each of thesidewall spacers;

(f) selectively introducing dopant impurities of a second, oppositeconductivity type into the exposed portions of the substrate surfaceadjacent each of the sidewall spacers to form a pair of spaced-apart,source/drain regions in the substrate, each of the pair of source/drainregions extending to just beneath a respective proximal edge of the gateelectrode; and

(g) removing residue and/or contaminants resulting from theanisotropically etching from the exposed portions of the substratesurface and from the top surface of the gate electrode.

In embodiments according to the present invention, step (g) is performedeither prior or subsequent to performing step (f); step (a) comprisesproviding a silicon wafer substrate; step (b) comprises forming asilicon oxide thin gate insulating layer about 25-50 Å thick; step (c)comprises forming the gate electrode from an electrically conductivematerial comprising heavily-doped polysilicon; step (d) comprisesforming a blanket layer of an insulative material comprising an oxide,nitride, or oxynitride of silicon of a preselected thickness forproviding each of the tapered sidewall spacers with a preselected widthat the wider bottom ends thereof adjacent the substrate surface; step(e) comprises anisotropically etching the blanket layer of insulatingmaterial in a reactive plasma comprising a fluorocarbon orfluorohydrocarbon compound selected from CF₄ and CHF₃; step (f)comprises selectively implanting the first conductivity type substratewith dopant-containing ions of second, opposite conductivity type; andstep (g) comprises removing a carbonaceous residue from the exposedportions of the substrate surface and the top surface of the gateelectrode by treatment with a H₂, H₂/N₂, or NH₃ plasma comprisingionized hydrogen.

According to a further embodiment of the present invention, the methodfurther comprises the steps of:

(h) forming a blanket layer of a metal in contact with at least theexposed portions of the substrate surface adjacent the sidewall spacers,the top surface of the gate electrode, and the sidewall spacers;

(i) reacting the blanket metal layer to selectively form an electricallyconductive silicide of the metal in contact with the exposed portions ofthe substrate surface adjacent the sidewall spacers and the top surfaceof the gate electrode; and

(j) selectively removing unreacted portions of the blanket metal layer,including portions in contact with the sidewall spacers.

According to embodiments of the present invention, step (h) comprisesforming the blanket metal layer from a refractory metal selected fromthe group consisting of platinum, titanium, cobalt, and nickel; and step(h) comprises thermally reacting the refractory metal layer withunderlying silicon of the substrate.

According to another aspect of the present invention, a method ofmanufacturing an MOS semiconductor device comprises the steps of:

(a) providing a silicon semiconductor wafer substrate having a surface;

(b) forming a thin silicon oxide gate insulator layer about 25-50 Åthick in contact with the substrate surface;

(c) forming a gate electrode comprising heavily-doped polysilicon on aportion of the thin gate insulating layer, the gate electrode comprisingfirst and second opposing side surfaces and a top surface;

(d) forming a blanket layer of an insulative material comprising anoxide, nitride, or oxynitride of silicon on the exposed portions of thethin gate insulator layer on the substrate surface and on the first andsecond opposing side surfaces and the top surface of the gate electrode;

(e) selectively removing, by anisotropically etching in a reactiveplasma comprising a fluorocarbon or fluorohydrocarbon compound, (1) theblanket layer of insulative material and underlying portions of the thingate insulator layer from the substrate surface, and (2) the blanketlayer of insulative material from the top surface of the gate electrode,thereby forming a tapered insulative sidewall spacer on each of thefirst and second opposing side surfaces of the gate electrode, withportions of the thin gate insulator layer remaining below the widerbottom ends of the tapered sidewall spacers adjacent the substratesurface and exposed portions of the substrate surface being formedadjacent each of the sidewall spacers;

(f) selectively ion implanting dopant impurities of a second, oppositeconductivity type into the exposed portions of the substrate surfaceadjacent each of the sidewall spacers to form a pair of spaced-apart,source/drain regions in the substrate, each of the pair of source/drainregions extending to just beneath a respective proximal edge of the gateelectrode;

(g) removing carbonaceous residue and/or contaminants resulting from theanisotropic reactive plasma etching from the exposed portions of thesubstrate surface adjacent the sidewall spacers and from the top surfaceof the gate electrode by treatment with a plasma comprising ionizedhydrogen;

(h) forming a blanket layer of a refractory metal selected from thegroup consisting of platinum, titanium, cobalt, and nickel in contactwith the exposed portions of the substrate surface adjacent the sidewallspacers, the top surface of the gate electrode, and the sidewallspacers;

(i) reacting the blanket metal layer to selectively form an electricallyconductive silicide of the metal at portions thereof in contact with theexposed portions of the silicon substrate surface adjacent the sidewallspacers and the top surface of the polysilicon gate electrode; and

(i) selectively removing unreacted portions of the blanket metal layer,including portions in contact with the insulative sidewall spacers.

In embodiments according to the present invention, step (g) is performedprior or subsequent to performing step (f) and the ionized hydrogenplasma comprises a H₂, H₂/N₂, or NH₃ plasma.

According to yet another aspect of the present invention, silicon-basedMOS-type transistor devices formed by the method of the above-enumeratedsteps (a)-(j) are provided.

Additional advantages and aspects of the present invention will becomereadily apparent to those skilled in the art from the following detaileddescription, wherein only the preferred embodiment of the presentinvention is shown and described, simply by way of illustration of thebest mode contemplated for carrying out the method of the presentinvention. As will be described, the present invention is capable ofother and different embodiments, and its several details are susceptibleof modification in various obvious respects, all without departing fromthe spirit of the present invention. Accordingly, the drawing anddescription are to be regarded as illustrative in nature, and not aslimitative.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description of the embodiment of the presentinvention can best be understood when read in conjunction with thefollowing drawings, in which like reference numerals are employedthroughout to designate similar features, wherein:

FIGS. 1(A)-1(E) illustrate, in simplified, cross-sectional schematicform, a sequence of steps for forming MOS type transistors utilizingsalicide technology according to conventional practices;

FIG. 2 illustrates, in simplified, cross-sectional schematic form, aplasma treatment step according to the inventive methodology forremoving surface residues and/or contaminants prior to the silicidationprocessing of FIG. 1(D); and

FIG. 3 illustrates, in simplified, cross-sectional schematic view, anMOS transistor comprising salicide source, gate, and drain contactsformed by the method of the present invention.

DESCRIPTION OF THE INVENTION

The present invention addresses and solves problems arising frommanufacturing submicron-dimensioned, ultra-shallow junction MOS and CMOStransistors suitable for use in high-density integration semiconductordevices, wherein, as part of the fabrication methodology, insulativesidewall spacers are formed by selective anisotropic etching of ablanket insulator layer, which sidewall spacers act as at least part ofan implantation mask during formation of moderately- to heavily-dopedsource/drain junction regions to which electrical contact is made by useof salicide technology. More specifically, the present inventionadvantageously provides a significant and substantial reduction in theamount and severity of spiking resulting from junction penetrationduring silicidation reaction performed as part of the salicideprocessing, which spiking deleteriously affects junction quality,typically manifested as increased junction leakage current. Moreover,the inventive methodology provides increased device reliability whiledecreasing product yield problems associated with the conventionaltechnology. In addition, the inventive method is fully compatible withother aspects of existing processing methodology.

Referring now to FIG. 2, which figure is analogous to FIG. 1(B)according to the conventional art described supra and illustrates thestate of a MOS device precursor after anisotropic selective etching ofblanket insulator layer 7 typically comprised of an oxide, nitride, oroxynitride of silicon, for forming insulative sidewall spacers 7′, 7′.As previously indicated, such anisotropic selective etching typicallycomprises reactive plasma etching utilizing a fluorocarbon- orfluorohydrocarbon-based plasma comprising at least one reactive,carbon-containing gaseous species selected from CF₄ and CHF₃. Thepresent invention is based upon recognition that such selectiveanisotropic reactive plasma etching utilizing fluorocarbon- and/orfluorohydrocarbon-based materials disadvantageously results in formationof a carbonaceous residue or contaminant 14 on at the exposed portionsof the substrate surface 4 adjacent sidewall spacers 7′, 7′ and the topsurface 6″ of gate electrode 6, which residue and/or contaminationcauses uneven silicidation reaction during subsequent processing,leading to junction penetration or spiking, as illustratively indicatedabove at 13 in FIG. 1(E).

Referring still to FIG. 2, according to the inventive methodology,subsequent to the selective anisotropic etching step of FIG. 1(B) forforming insulative sidewall spacers 7′, 7′, the MOS precursor structureis subjected to a plasma treatment for removal of the carbonaceousresidue and/or contamination 14 from the exposed portions of thesubstrate surface 4 adjacent the sidewall spacers 7′, 7′ and from thetop surface 6″ of gate electrode 6. Such plasma treatment is preferablyperformed prior to implantation of the exposed substrate surfaceportions for source/drain formation; however, it is within the spirit ofthe present invention to perform the plasma treatment subsequent tosource/drain ion implantation. By way of illustration, but notlimitation, removal of carbonaceous residue 14 may be effected bytreating the exposed substrate surface portions adjacent the sidewallspacers and the top surface of the gate electrode to a plasma comprisingionized hydrogen, e.g., as is obtained with gases or gas mixturesselected from H₂, H₂/N₂, and NH₃. Hydrogen ion-containing plasmas foruse in the present invention may be generated in any conventionalmanner, e.g., as by DC, AC, or RF excitation. Given the presentdisclosure and the objectives of the present invention, suitableparameters for complete removal of residue 14 (as determined byconventional analytical methods not described herein for brevity) bysuch plasma treatment, e.g., gas pressure, power density, treatmentduration, etc., may be optimized for use in particular situations. Byway of illustration, but not limitation, plasma conditions suitable foruse in the present invention include: DC or RF excitation at 100-1,000W, H₂ gas pressures of 100-300 mTorr, and treatment times of 20-400 sec.

Upon completion of the plasma treatment for removal of carbonaceousresidue 14, salicide reaction proceeds in conventional manner, e.g., asillustrated in FIGS. 1(C)-1E), described supra, for forming MOS-typetransistors including metal silicide-contacted moderately- toheavily-doped source and drain regions 8, 9, along with respectivelightly-doped, shallow-depth, source and drain extensions 8′, 9′. As maybe evident from FIG. 3, MOS-type transistors formed according to theinventive methodology are substantially free of the junction penetrationor spiking associated with the conventional methodology, e.g., as shownat 13 in FIG. 1(E). As a consequence, MOS-type devices fabricatedaccording to the method of the present invention exhibit reducedjunction leakage currents as compared with similar devices obtained viaconventional methodology.

The present invention thus enables formation of reliable, defect-free,low junction leakage, submicron-dimensioned MOS transistors and CMOSdevices at rates consistent with the requirements of manufacturingthroughput, and is fully compatible with conventional process flow forautomated manufacture of high-density integration semiconductor devices.

In the previous description, numerous specific details are set forth,such as specific materials. structures, reactants, processes, etc. inorder to provide a better understanding of the present invention.However, the present invention can be practiced without resorting to thedetails specifically set forth. In other instances, well-knownprocessing materials and techniques have not been described in order notto unnecessarily obscure the present invention.

Only the preferred embodiment of the present invention and but a fewexamples of its versatility are shown and described in the presentdisclosure. It is to be understood that the present invention is capableof use in various other combinations and environments and is susceptibleof changes or modifications within the scope of the inventive concept asexpressed herein.

What is claimed is:
 1. A method of manufacturing a semiconductor device,which method comprises the steps of: (a) providing a semiconductorsubstrate of a first conductivity type and having a surface; (b) forminga thin gate insulator layer in contact with said substrate surface; (c)forming a gate electrode on a portion of said gate insulator layer, saidgate electrode comprising first and second opposing side surfaces and atop surface; (d) forming a blanket layer of an insulative material onthe exposed portions of said thin gate insulator layer on said substratesurface and on said first and second opposing side surfaces and said topsurface of said gate electrode; (e) selectively removing, byanisotropically etching, (1) said blanket layer of insulative materialand underlying portions of said thin gate insulator layer from saidsubstrate surface, and (2) said blanket layer of insulative materialfrom said top surface of said gate electrode, thereby forming a taperedinsulative sidewall spacer on each of said first and second opposingside surfaces of said gate electrode, with portions of said thin gateinsulator layer remaining below the wider bottom ends of said taperedsidewall spacers adjacent said substrate surface and exposed portions ofsaid substrate surface being formed adjacent each of said sidewallspacers; (f) selectively introducing dopant impurities of a second,opposite conductivity type into said exposed portions of said substratesurface adjacent each of said sidewall spacers to form a pair ofspaced-apart, source/drain regions in said substrate, each of said pairof source/drain regions extending to just beneath a respective proximaledge of said gate electrode; and (g) removing residue and/orcontaminants resulting from said anisotropically etching from saidexposed portions of said substrate surface adjacent said sidewallspacers and from said top surface of said gate electrode.
 2. The methodas in claim 1, comprising performing step (g) after step (e) and priorto performing step (f).
 3. The method as in claim 1, comprisingperforming step (g) after performing steps (e) and (f).
 4. The method asin claim 1, wherein step (a) comprises providing a silicon wafersubstrate.
 5. The method as in claim 4, wherein step (b) comprisesforming a silicon oxide thin gate insulating layer about 25-50 Å thick.6. The method as in claim 5, wherein step (c) comprises forming saidgate electrode from an electrically conductive material comprisingheavily-doped polysilicon.
 7. The method as in claim 6, wherein step (d)comprises forming a blanket layer of an insulative material comprisingan oxide, nitride, or oxynitride of silicon of a preselected thicknessfor providing each of said tapered insulative spacers with a preselectedwidth at said wider bottom ends thereof adjacent said substrate surface.8. The method as in claim 7, wherein step (e) comprises anisotropicallyetching said blanket layer of insulative material in a reactive plasmacomprising a fluorocarbon or fluorohydrocarbon compound.
 9. The methodas in claim 8, wherein said fluorocarbon or fluorohydrocarbon compoundis selected from the group consisting of CF₄ and CHF₃.
 10. The method asin claim 8, wherein step (g) comprises removing a carbonaceous residueand/or contaminant from said exposed portions of said substrate surfaceadjacent said sidewall spacers and from said top surface of said gateelectrode.
 11. The method as in claim 10, comprising removing saidcarbonaceous residue by treating said exposed portions of said substratesurface adjacent said sidewall spacers and said top surface of said gateelectrode with a plasma.
 12. The method as in claim 11, wherein saidplasma comprises an ionized hydrogen plasma.
 13. The method as in claim12, wherein said plasma comprises a H₂, H₂/N₂, or NH₃ plasma.
 14. Themethod as in claim 7, further comprising the steps of: (h) forming ablanket layer of a metal in contact with at least said exposed portionsof said substrate surface adjacent said sidewall spacers, said topsurface of said gate electrode, and said sidewall spacers; (i) reactingsaid blanket metal layer to selectively form an electrically conductivesilicide of said metal at portions thereof in contact with said exposedportions of said substrate surface adjacent said sidewall spacers andsaid top surface of said gate electrode; and (j) selectively removingunreacted portions of said blanket metal layer, including portions incontact with said sidewall spacers.
 15. The method as in claim 14,wherein step (h) comprises forming said blanket metal layer from arefractory metal selected from the group consisting of platinum,titanium, cobalt, and nickel; and step (i) comprises thermally reactingsaid refractory metal layer with underlying silicon of said substrate.16. The method as in claim 4, wherein step (f) comprises selectivelyimplanting said first conductivity type substrate with dopant-containingions of second, opposite conductivity type.
 17. A method ofmanufacturing an MOS semiconductor device, which method comprises thesteps of: (a) providing a silicon semiconductor wafer substrate of firstconductivity type and having a surface; (b) forming a thin silicon oxidegate insulator layer about 25-50 Å thick in contact with said substratesurface; (c) forming a gate electrode comprising heavily-dopedpolysilicon on a portion of said thin gate insulator layer, said gateelectrode comprising first and second opposing side surfaces and a topsurface; (d) forming a blanket layer of an insulative materialcomprising an oxide, nitride, or an oxynitride of silicon on the exposedportions of said thin gate insulator layer on said substrate surface andon said first and second opposing side surfaces and said top surface ofsaid gate electrode; (e) selectively removing, by anisotropicallyetching in a reactive plasma comprising a fluorocarbon orfluorohydrocarbon compound, (1) said blanket layer of insulativematerial and underlying portions of said thin gate insulator layer fromsaid substrate surface, and (2) said blanket layer of insulativematerial from said top surface of said gate electrode, thereby forming atapered insulative sidewall spacer on each of said first and secondopposing side surfaces of said gate electrode, with portions of saidthin gate insulator layer remaining below the wider bottom ends of saidtapered sidewall spacers adjacent said substrate surface and exposedportions of said substrate surface being formed adjacent each of saidsidewall spacers; (f) selectively ion implanting dopant impurities of asecond, opposite conductivity type into said exposed portions of saidsubstrate surface adjacent each of said sidewall spacers to form a pairof spaced-apart, source/drain regions in said substrate, each of saidpair of source/drain regions extending to just beneath a respectiveproximal edge of said gate electrode; (g) removing carbonaceous residueand/or contaminants resulting from said anisotropic reactive plasmaetching from said exposed portions of said substrate surface adjacentsaid sidewall spacers and from said top surface of said gate electrodeby treatment with a plasma comprising ionized hydrogen; (h) forming ablanket layer of a refractory metal selected from the group consistingof platinum, titanium, cobalt, and nickel in contact with said exposedportions of said substrate surface adjacent said sidewall spacers, saidtop surface of said gate electrode, and said sidewall spacers; (i)reacting said blanket metal layer to selectively form an electricallyconductive silicide of said metal at portions thereof in contact withsaid exposed portions of said silicon substrate surface adjacent saidsidewall spacers and said top surface of said polysilicon gateelectrode; and (j) selectively removing unreacted portions of saidblanket metal layer, including portions in contact with said sidewallspacers.
 18. The method as in claim 17, comprising performing step (g)prior or subsequent to performing step (f).
 19. The method as in claim17, wherein said ionized hydrogen plasma comprises a H₂, H₂/N₂, or NH₃plasma.
 20. A silicon-based MOS transistor device formed according tothe method of claim 17.